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EIA JESD 217.01:2016

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EIA JESD 217.01:2016

Test Methods to Characterize Voiding in Pre-SMT Ball Grid Array Packages

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This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Test methods can be applied to several types of ball grid array packages such as FCBGA, PBGA, CBGA, and CCGA with minimum 0.5 mm ball-to-ball pitch and constructed with leaded and lead-free solder alloys. Guidelines for pre-SMT voids may not be sufficiently robust where ball grid array packages balls are assembled onto unfilled micro-via structures on package substrate land.

Author EIA
Editor EIA
Document type Standard
Format File
ICS 31.200 : Integrated circuits. Microelectronics
Number of pages 46
Replace EIA JESD 217 (2010-09)
Year 2016
Document history EIA JESD 217.01 (2016-10)
Country USA
Keyword EIA JESD 217;EIA 217;EIA 217.01;217;EIA JESD217.01