EIA JESD 214.01:2017

This document describes a constant temperature (isothermal) aging method for testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditions, the method may be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time. Dual damascene Cu metallization systems usually have liners, such as tantalum (Ta) or tantalum nitride (TaN) on the bottom and sides of trenches etched into dielectric layers. Hence, for structures in which a single via contacts a wide line below it, a void under the via can cause an open circuit at almost the same time as any percentage resistance shift that would satisfy a failure criterion. The method assumes that void growth (and therefore resistance changes) can be modeled as described by Ogawa, et al.[1], Yao, et all [2, 3] Fischer et al. [5,6], to obtain a median lifetime, an effective activation energy, and an acceleration factor for lifetime.