EIA JEP 155B:2018

The intent of this report is to document and provide critical information to assess and make decisions on safe ESD level requirements. The scope of this document is to provide this information to quality organizations in both semiconductor companies and their IC customers. Special Notes on the System Level ESD: This work and the recommendations therein are intended for Component Level safe ESD requirements and will have little or no effect on system level ESD results. Systems and System boards should continue to be designed to meet appropriate ESD threats regardless of the components in the systems that are meeting the new recommendations from this work, and that all proper system reliability must be assessed through the IEC test method. Special Notes on the Machine Model: The machine model (MM) method as specified by some customers and suppliers is not a qualification methodology by JEDEC for use in place of or in addition to HBM and CDM test qualification.