EIA JEP 171:2014

This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5. This document provides the test methodology details on: 1. CK and WCK Timings: tCK, tWCK, tCH/tCL, tWCKH/tWCKL, CK TJ/RJrms, CK and WCK Jitter 2. CK and WCK Input Operating Conditions: VIXCK, VIXWCK, VIDCK(ac), VIDWCK(ac), VIDCK(dc), VIDWCK(dc), CKslew, and WCKslew 3. Data Input Timings: tDIVW, tDIPW NOTE The procedures described in this document are intended to provide information about the tests that will be used in JEDEC GDDR5 recommended measurement parameter. This testing is not a replacement for an exhaustive test validation plan.